Packaging is one of the final steps in the process of manufacturing integrated semiconductor circuit components or chips. In packaging, a fabricated semiconductor chip is mounted in a protective housing. After packaging, the assembled component is subjected to final testing and then connected to an electronic circuit.
Currently, many semiconductor chips are contained in plastic packages. These packages are provided with reinforced metal leads for electrically connecting the chip to the printed circuit board which contains the circuit in which the chip is to be included. Within the package, one end of each lead is connected to a specific bonding point on the chip, usually by an intermediate lead; the other end of the lead, which extends outside of the package, is attached to a connection on the printing circuit board.
Recently, advances in semiconductor manufacturing technology have made the fabrication of Very Large Scale Integration (VLSI) chips possible. VLSI chips comprise a large number of individual circuit components that are fabricated together on a single, very small chip. VLSI chips are able to perform a large number of electrical functions, and perform them more rapidly, than was previously possible.
To date, it has been difficult to provide suitable packaging for VLSI chips. In part, this is because each chip requires a large number of connections to external circuit elements. Many VLSI chips have 100 to over 300 bonding points each of which must be connected to a lead for connection to external circuit elements.
Another consideration in the use of a VLSI chip is the need to provide common voltages to a number of different locations on the chip. For instance, a chip that comprises a number of individual transistors, such as C-MOS type transistors, may require a common drain voltage supplied by an external power supply that is applied to the drain terminals of all the transistors, and a common source voltage also provided by an external power supply applied to the source terminals of all the transistors. Typically the drain voltage is positive with respect to a common reference or ground voltage, and the source voltage is typically at the same level as the ground voltage. The common voltages need to be supplied to the chip so the individual components all operate with respect to a common power level. Normally, common voltages are supplied to the components on the chip by providing sets of leads, each set designed to carry the same voltage, to different bond points on the chip.
Providing a VLSI chip with a common voltage at a number of locations has, to date, been a difficult task. In a VLSI package, the leads which are connected to the chip are spaced closely together. Moreover, some of the leads supply voltages such as signal voltages that fluctuate rapidly as electronic functions are performed on them by the chip and the other circuit components. This causes the magnetic field normally developed around these leads to vary, which in turn, causes an inductive current to flow in adjacent leads. Whenever a sufficiently large inductive current is developed in a common voltage lead, the voltage it is carrying changes. This problem may be intensified because in a VLSI chip such as a digital logic chip, voltages may fluctuate rapidly, this rapid change intensifies the development of a magnetic field and the associated inductive current flow. As a result, the voltage supplied to one or more components on the VLSI chip may vary so greatly as to cause the chip to malfunction.
There have been some attempts at providing packages for VLSI chips that are designed to minimize the problems associated with the development of inductive current flow. One such package is a multi-layered ceramic package. This package includes layers of conductors separated by layers of dielectric ceramic that are pressed together. A cavity is formed in the layers, and the chip is mounted in the cavity. Wire bonds are used to connect the bond points on the chip to the individual conductors on the top layer of conductors. Individual wire bonds or reinforced metal leads are used to provide an electrical connection to the printed circuit board the chip is attached to. Selected top-layer conductors, which carry common voltages, are connected to common intermediate-layer conductors. The intermediate-layer conductors function as reference voltage planes which insure the common voltages supplied through the top-layer conductors attached thereto does not appreciably vary.
However, there are a number of limitations associated with multi-layer ceramic packages. The size of these packages tends to be extremely large in order to accommodate the interconnections needed between the conductor layers. Moreover, a multi-layered ceramic package designed to contain a VLSI chip is expensive to manufacture. In some instances, the cost of the multi-layered ceramic package may significantly exceed the cost of fabricating the chip.